1. Field of the Invention
The present invention relates to a silicon-on-insulator (SOI) substrate and a semiconductor integrated circuit (IC) device with reduced noise. In particular, the present invention relates to an SOI substrate and an SOI IC device for realizing larger packing density of elements.
2. Description of the Related Art
In a hitherto developed SOI technology, a buried oxide (BOX) layer is formed on a silicon substrate, an SOI layer is formed on the BOX layer, and an IC including a MOS transistor or the like is formed in the SOI layer. With this technology, a MOS transistor can be driven at high speed (for example, Patent Document 1: Japanese Unexamined Patent Application Publication No. 2001-339071).
Recently, however, an operating frequency of semiconductor IC devices has been extremely high and a greater area has been allocated for power-supply wiring and ground wiring. When a semiconductor IC device is operated at high frequency, fluctuations in power-supply voltage including a temporary current spike are likely to occur. Also, noise may propagate from a circuit to another in an IC including a plurality of circuits, so that a malfunction may occur in the IC.
In order to suppress fluctuations in power-supply voltage, a technology of connecting a decoupling capacitor to a power supply in parallel has been used. With this technology, power noise can be reduced and fluctuations in power-supply voltage can be suppressed, and thus a malfunction of a semiconductor IC caused by power noise and fluctuations in power-supply voltage can be prevented. In order to achieve the purpose, the capacitance of a decoupling capacitor connected to the power supply must be several tens of nF to each chip or package. In a known semiconductor IC device, a dedicated area for placing a decoupling capacitor is provided in each side between a core portion, which is an element formation area, and an I/O portion, and a decoupling capacitor is formed by using metal oxide semiconductor (MOS).
In this known semiconductor IC device, however, a dedicated area for a decoupling capacitor must be provided, and thus the area of the device increases. Accordingly, the packing density of elements decreases disadvantageously.
In order to overcome this problem, another technology has been disclosed. That is, a polycrystalline silicon layer is formed at a side of an element on a semiconductor substrate in an element formation area, and a decoupling capacitor is formed between the polycrystalline silicon layer and a diffusion layer formed on the surface of the semiconductor substrate (for example, Patent Document 2: Japanese Unexamined Patent Application Publication No. 10-12825 (P.3 and FIGS. 1 and 2)). Patent Document 2 describes that a dedicated area for a decoupling capacitor is unnecessary in this configuration.
In this known art, however, the decoupling capacitor is formed at a side of the element in the element formation area, and thus the element formation area increases disadvantageously.
Also, a technology of providing a multilayer wiring structure on a semiconductor element and forming an electrode, a dielectric layer, and an electrode thereon in this order so as to form a decoupling capacitor, has been disclosed (for example, Patent Document 3: Japanese Unexamined Patent Application Publication No. 2002-124636 (PP.3-5 and FIG. 7)). Patent Document 3 describes that a large-capacitance decoupling capacitor can be provided in the semiconductor device.
On the other hand, a technology of providing a guard ring for encircling a circuit susceptible to noise has been known (for example, Patent Document 4: Japanese Unexamined Patent Application Publication No. 2001-044277). This technology is used for preventing noise from propagating from a circuit to another.
In the technology described in Patent Document 3, however, since the decoupling capacitor is provided on the multilayer wiring structure, a pad electrode or the like cannot be provided in the area provided with the decoupling capacitor on the multilayer wiring structure. Therefore, layout freedom in the semiconductor IC device is restricted and thus the size of the device increases. Furthermore, in order to provide the decoupling capacitor on the multilayer wiring structure, at least a step of forming a lower-layer electrode, a step of forming a dielectric layer, and a step of forming an upper-layer electrode are necessary. As a result, a process of fabricating semiconductor IC devices becomes complicated and the fabrication cost increases.
Also, in the technology of providing a guard ring described in Patent Document 4, by providing a guard ring so as to encircle a circuit, the element formation area increases disadvantageously.